// ******************************************************************************
// Copyright     :  Copyright (C) 2016, Hisilicon Technologies Co. Ltd.
// File name     :  c_union_define_CRG.h
// Project line  :  IT Product Line
// Department    :  ICT Processor Chipset Development Department
// Version       :  V100
// Date          :  2014/5/8
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.0.2.5
// History       :   2016/08/17 15:16:31 Create file
// ******************************************************************************

#ifndef C_UNION_DEFINE_CRG_H
#define C_UNION_DEFINE_CRG_H

/* Define the union u_crg_pll_cfg0 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int pll0_frac : 24;         /* [23..0]  */
        unsigned int pll0_fout4phasepd : 1;  /* [24]  */
        unsigned int pll0_foutvcopd : 1;     /* [25]  */
        unsigned int pll0_foutpostdivpd : 1; /* [26]  */
        unsigned int pll0_dsmpd : 1;         /* [27]  */
        unsigned int pll0_dacpd : 1;         /* [28]  */
        unsigned int pll0_bypass : 1;        /* [29]  */
        unsigned int pll0_pd : 1;            /* [30]  */
        unsigned int pll0_dbg : 1;           /* [31]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_pll_cfg0;

/* Define the union u_crg_pll_cfg1 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int pll1_frac : 24;         /* [23..0]  */
        unsigned int pll1_fout4phasepd : 1;  /* [24]  */
        unsigned int pll1_foutvcopd : 1;     /* [25]  */
        unsigned int pll1_foutpostdivpd : 1; /* [26]  */
        unsigned int pll1_dsmpd : 1;         /* [27]  */
        unsigned int pll1_dacpd : 1;         /* [28]  */
        unsigned int pll1_bypass : 1;        /* [29]  */
        unsigned int pll1_pd : 1;            /* [30]  */
        unsigned int pll1_dbg : 1;           /* [31]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_pll_cfg1;

/* Define the union u_crg_pll_cfg2 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int pll2_frac : 24;         /* [23..0]  */
        unsigned int pll2_fout4phasepd : 1;  /* [24]  */
        unsigned int pll2_foutvcopd : 1;     /* [25]  */
        unsigned int pll2_foutpostdivpd : 1; /* [26]  */
        unsigned int pll2_dsmpd : 1;         /* [27]  */
        unsigned int pll2_dacpd : 1;         /* [28]  */
        unsigned int pll2_bypass : 1;        /* [29]  */
        unsigned int pll2_pd : 1;            /* [30]  */
        unsigned int pll2_dbg : 1;           /* [31]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_pll_cfg2;

/* Define the union u_crg_pll_cfg3 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int pll3_frac : 24;         /* [23..0]  */
        unsigned int pll3_fout4phasepd : 1;  /* [24]  */
        unsigned int pll3_foutvcopd : 1;     /* [25]  */
        unsigned int pll3_foutpostdivpd : 1; /* [26]  */
        unsigned int pll3_dsmpd : 1;         /* [27]  */
        unsigned int pll3_dacpd : 1;         /* [28]  */
        unsigned int pll3_bypass : 1;        /* [29]  */
        unsigned int pll3_pd : 1;            /* [30]  */
        unsigned int pll3_dbg : 1;           /* [31]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_pll_cfg3;

/* Define the union u_crg_pll_cfg4 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int pll4_frac : 24;         /* [23..0]  */
        unsigned int pll4_fout4phasepd : 1;  /* [24]  */
        unsigned int pll4_foutvcopd : 1;     /* [25]  */
        unsigned int pll4_foutpostdivpd : 1; /* [26]  */
        unsigned int pll4_dsmpd : 1;         /* [27]  */
        unsigned int pll4_dacpd : 1;         /* [28]  */
        unsigned int pll4_bypass : 1;        /* [29]  */
        unsigned int pll4_pd : 1;            /* [30]  */
        unsigned int pll4_dbg : 1;           /* [31]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_pll_cfg4;

/* Define the union u_crg_pll_cfg5 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int pll5_frac : 24;         /* [23..0]  */
        unsigned int pll5_fout4phasepd : 1;  /* [24]  */
        unsigned int pll5_foutvcopd : 1;     /* [25]  */
        unsigned int pll5_foutpostdivpd : 1; /* [26]  */
        unsigned int pll5_dsmpd : 1;         /* [27]  */
        unsigned int pll5_dacpd : 1;         /* [28]  */
        unsigned int pll5_bypass : 1;        /* [29]  */
        unsigned int pll5_pd : 1;            /* [30]  */
        unsigned int pll5_dbg : 1;           /* [31]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_pll_cfg5;

/* Define the union u_crg_pll_div0 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int pll0_fbdiv : 12;     /* [11..0]  */
        unsigned int pll0_refdiv : 6;     /* [17..12]  */
        unsigned int pll0_postdiv2 : 3;   /* [20..18]  */
        unsigned int pll0_postdiv1 : 3;   /* [23..21]  */
        unsigned int pll0_acg_enable : 1; /* [24]  */
        unsigned int pll0_acg_update : 1; /* [25]  */
        unsigned int reserved_0 : 6;      /* [31..26]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_pll_div0;

/* Define the union u_crg_pll_div1 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int pll1_fbdiv : 12;   /* [11..0]  */
        unsigned int pll1_refdiv : 6;   /* [17..12]  */
        unsigned int pll1_postdiv2 : 3; /* [20..18]  */
        unsigned int pll1_postdiv1 : 3; /* [23..21]  */
        unsigned int reserved_0 : 8;    /* [31..24]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_pll_div1;

/* Define the union u_crg_pll_div2 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int pll2_fbdiv : 12;   /* [11..0]  */
        unsigned int pll2_refdiv : 6;   /* [17..12]  */
        unsigned int pll2_postdiv2 : 3; /* [20..18]  */
        unsigned int pll2_postdiv1 : 3; /* [23..21]  */
        unsigned int reserved_0 : 8;    /* [31..24]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_pll_div2;

/* Define the union u_crg_pll_div3 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int pll3_fbdiv : 12;   /* [11..0]  */
        unsigned int pll3_refdiv : 6;   /* [17..12]  */
        unsigned int pll3_postdiv2 : 3; /* [20..18]  */
        unsigned int pll3_postdiv1 : 3; /* [23..21]  */
        unsigned int reserved_0 : 8;    /* [31..24]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_pll_div3;

/* Define the union u_crg_pll_div4 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int pll4_fbdiv : 12;   /* [11..0]  */
        unsigned int pll4_refdiv : 6;   /* [17..12]  */
        unsigned int pll4_postdiv2 : 3; /* [20..18]  */
        unsigned int pll4_postdiv1 : 3; /* [23..21]  */
        unsigned int reserved_0 : 8;    /* [31..24]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_pll_div4;

/* Define the union u_crg_pll_div5 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int pll5_fbdiv : 12;   /* [11..0]  */
        unsigned int pll5_refdiv : 6;   /* [17..12]  */
        unsigned int pll5_postdiv2 : 3; /* [20..18]  */
        unsigned int pll5_postdiv1 : 3; /* [23..21]  */
        unsigned int reserved_0 : 8;    /* [31..24]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_pll_div5;

/* Define the union u_crg_sys_clk_cfg0 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int dp_clk_sel : 1;       /* [0]  */
        unsigned int up_clk_sel : 1;       /* [1]  */
        unsigned int cp_clk_sel : 1;       /* [2]  */
        unsigned int ahb_clk_sel : 1;      /* [3]  */
        unsigned int apb_clk_sel : 1;      /* [4]  */
        unsigned int sfc_clk_sel : 1;      /* [5]  */
        unsigned int itf_clk_sel : 1;      /* [6]  */
        unsigned int ncsi_mac_clk_sel : 1; /* [7]  */
        unsigned int mag_an_clk_sel : 1;   /* [8]  */
        unsigned int lcam_clk_sel : 1;     /* [9]  */
        unsigned int fic_ref_clk_sel : 1;  /* [10]  */
        unsigned int reserved_0 : 21;      /* [31..11]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_sys_clk_cfg0;

/* Define the union u_crg_sys_clk_en0 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int lcam_clk_en : 5;           /* [4..0]  */
        unsigned int cp_clk_en : 1;             /* [5]  */
        unsigned int dp_clk_en : 1;             /* [6]  */
        unsigned int dcip_clk_en : 1;           /* [7]  */
        unsigned int itf_clk_en : 1;            /* [8]  */
        unsigned int lcam_common_clk_en : 1;    /* [9]  */
        unsigned int arm_clk_en : 1;            /* [10]  */
        unsigned int mag_dp_clk_en : 1;         /* [11]  */
        unsigned int fic_dp_clk_en : 1;         /* [12]  */
        unsigned int sys_spi_clk_en : 1;        /* [13]  */
        unsigned int sys_pie_clk_en : 1;        /* [14]  */
        unsigned int sys_ncsi_clk_en : 1;       /* [15]  */
        unsigned int sml1_clk_en : 1;           /* [16]  */
        unsigned int sml0_clk_en : 1;           /* [17]  */
        unsigned int ckd_clk_en : 1;            /* [18]  */
        unsigned int fic_ref_clk_en : 1;        /* [19]  */
        unsigned int fic_sync_clk_en : 1;       /* [20]  */
        unsigned int mag_cfg_clk_en : 1;        /* [21]  */
        unsigned int mag_ptp_clk_en : 1;        /* [22]  */
        unsigned int fic_cp_clk_en : 1;         /* [23]  */
        unsigned int fic_cfg_clk_en : 1;        /* [24]  */
        unsigned int pcie_pcs_apb_clk_en : 1;   /* [25]  */
        unsigned int pcie_sw_apb_clk_en : 1;    /* [26]  */
        unsigned int pcie_core_apb_clk_en : 1;  /* [27]  */
        unsigned int iocfg_apb_clk_en : 1;      /* [28]  */
        unsigned int pcie_sw_dev_clk_en : 1;    /* [29]  */
        unsigned int pcie_pcs_local_clk_en : 1; /* [30]  */
        unsigned int reserved_0 : 1;            /* [31]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_sys_clk_en0;

/* Define the union u_crg_sys_rst_req0 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int lcam_rst_req : 5;          /* [4..0]  */
        unsigned int cp_rst_req : 1;            /* [5]  */
        unsigned int dp_rst_req : 1;            /* [6]  */
        unsigned int dcip_rst_req : 1;          /* [7]  */
        unsigned int itf_rst_req : 1;           /* [8]  */
        unsigned int lcam_common_rst_req : 1;   /* [9]  */
        unsigned int reserved_0 : 1;            /* [10]  */
        unsigned int mag_dp_rst_req : 1;        /* [11]  */
        unsigned int fic_dp_rst_req : 1;        /* [12]  */
        unsigned int sys_spi_rst_req : 1;       /* [13]  */
        unsigned int sys_pie_rst_req : 1;       /* [14]  */
        unsigned int sys_ncsi_rst_req : 1;      /* [15]  */
        unsigned int sml1_rst_req : 1;          /* [16]  */
        unsigned int sml0_rst_req : 1;          /* [17]  */
        unsigned int ckd_rst_req : 1;           /* [18]  */
        unsigned int fic_ref_rst_req : 1;       /* [19]  */
        unsigned int fic_sync_rst_req : 1;      /* [20]  */
        unsigned int mag_cfg_rst_req : 1;       /* [21]  */
        unsigned int reserved_1 : 1;            /* [22]  */
        unsigned int fic_cp_rst_req : 1;        /* [23]  */
        unsigned int fic_cfg_rst_req : 1;       /* [24]  */
        unsigned int pcie_pcs_apb_rst_req : 1;  /* [25]  */
        unsigned int pcie_sw_apb_rst_req : 1;   /* [26]  */
        unsigned int pcie_core_apb_rst_req : 1; /* [27]  */
        unsigned int iocfg_apb_rst_req : 1;     /* [28]  */
        unsigned int pcie_sw_dev_rst_req : 1;   /* [29]  */
        unsigned int reserved_2 : 1;            /* [30]  */
        unsigned int mag_rst_req : 1;           /* [31]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_sys_rst_req0;

/* Define the union u_crg_sys_clk_cfg1 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int sfc_clk_div : 5;       /* [4..0]  */
        unsigned int up_clk_cfg : 1;        /* [5]  */
        unsigned int dp_clk_cfg : 1;        /* [6]  */
        unsigned int cp_clk_cfg : 1;        /* [7]  */
        unsigned int lcam_clk_div : 4;      /* [11..8]  */
        unsigned int fmag_rcd0_pd : 1;      /* [12]  */
        unsigned int fmag_rcd0_drv : 3;     /* [15..13]  */
        unsigned int fmag_rcd1_pd : 1;      /* [16]  */
        unsigned int fmag_rcd1_drv : 3;     /* [19..17]  */
        unsigned int ckd_clk_sel : 2;       /* [21..20]  */
        unsigned int fic_sync_clk_cfg : 2;  /* [23..22]  */
        unsigned int mbist_fun_clk_div : 8; /* [31..24]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_sys_clk_cfg1;

/* Define the union u_crg_sys_clk_en1 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int i2c_clk_en : 5;      /* [4..0]  */
        unsigned int led_clk_en : 1;      /* [5]  */
        unsigned int temp_clk_en : 1;     /* [6]  */
        unsigned int apb2ff_clk_en : 1;   /* [7]  */
        unsigned int mdio_clk_en : 5;     /* [12..8]  */
        unsigned int avs_clk_en : 1;      /* [13]  */
        unsigned int smb_clk_en : 1;      /* [14]  */
        unsigned int uart_clk_en : 1;     /* [15]  */
        unsigned int gpio_clk_en : 4;     /* [19..16]  */
        unsigned int smeg_clk_en : 4;     /* [23..20]  */
        unsigned int fmag_ahb_clk_en : 1; /* [24]  */
        unsigned int pcie_ahb_clk_en : 1; /* [25]  */
        unsigned int ncsi_mac_clk_en : 1; /* [26]  */
        unsigned int reserved_0 : 1;      /* [27]  */
        unsigned int ncsi_clk_en : 1;     /* [28]  */
        unsigned int tile0_clk_en : 1;    /* [29]  */
        unsigned int tile1_clk_en : 1;    /* [30]  */
        unsigned int smf_clk_en : 1;      /* [31]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_sys_clk_en1;

/* Define the union u_crg_sys_rst_req1 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int i2c_rst_req : 5;      /* [4..0]  */
        unsigned int led_rst_req : 1;      /* [5]  */
        unsigned int reserved_0 : 1;       /* [6]  */
        unsigned int apb2ff_rst_req : 1;   /* [7]  */
        unsigned int mdio_rst_req : 5;     /* [12..8]  */
        unsigned int avs_rst_req : 1;      /* [13]  */
        unsigned int smb_rst_req : 1;      /* [14]  */
        unsigned int uart_rst_req : 1;     /* [15]  */
        unsigned int gpio_rst_req : 4;     /* [19..16]  */
        unsigned int smeg_rst_req : 4;     /* [23..20]  */
        unsigned int reserved_1 : 1;       /* [24]  */
        unsigned int reserved_2 : 1;       /* [25]  */
        unsigned int ncsi_mac_rst_req : 1; /* [26]  */
        unsigned int spi_rst_req : 1;      /* [27]  */
        unsigned int ncsi_rst_req : 1;     /* [28]  */
        unsigned int tile0_rst_req : 1;    /* [29]  */
        unsigned int tile1_rst_req : 1;    /* [30]  */
        unsigned int smf_rst_req : 1;      /* [31]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_sys_rst_req1;

/* Define the union u_crg_sys_clk_en2 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int cpi_itf_clk_en : 1; /* [0]  */
        unsigned int mqm_itf_clk_en : 1; /* [1]  */
        unsigned int reserved_0 : 30;    /* [31..2]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_sys_clk_en2;

/* Define the union u_crg_pcie_hilink_rst */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int pcie_grstb_rst_req : 4; /* [3..0]  */
        unsigned int pcie_ahb_rst_req : 4;   /* [7..4]  */
        unsigned int pcie_perstn_enable : 4; /* [11..8]  */
        unsigned int pcie_perstn_clear : 4;  /* [15..12]  */
        unsigned int reserved_0 : 16;        /* [31..16]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_pcie_hilink_rst;

/* Define the union u_crg_pcie_clk_cfg0 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int pcie_mclk_div_rst_req : 4; /* [3..0]  */
        unsigned int reserved_0 : 28;           /* [31..4]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_pcie_clk_cfg0;

/* Define the union u_crg_pcie_clk_en0 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int pcie_lane_clk_en : 16; /* [15..0]  */
        unsigned int reserved_0 : 16;       /* [31..16]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_pcie_clk_en0;

/* Define the union u_crg_pcie_rst_req0 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int pcie_lane_rst_req : 16;   /* [15..0]  */
        unsigned int pcie_sticky_rst_req : 4;  /* [19..16]  */
        unsigned int pcie_port_rst_req : 4;    /* [23..20]  */
        unsigned int pcie_pcs_sft_rst_req : 1; /* [24]  */
        unsigned int pcie_sft_rst_req : 1;     /* [25]  */
        unsigned int reserved_0 : 6;           /* [31..26]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_pcie_rst_req0;

/* Define the union u_crg_pcie_obs_cfg */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int pcie_obs_clk_sel : 5;   /* [4..0]  */
        unsigned int pcie_obs_rst_req : 1;   /* [5]  */
        unsigned int pcie_probe_rst_req : 1; /* [6]  */
        unsigned int reserved_0 : 25;        /* [31..7]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_pcie_obs_cfg;

/* Define the union u_crg_status0 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int pll_lock : 6;      /* [5..0]  */
        unsigned int pll_loss_lock : 6; /* [11..6]  */
        unsigned int reserved_0 : 20;   /* [31..12]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_status0;

/* Define the union u_crg_top_obs_cfg */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int top_obs_clk_sel : 5;   /* [4..0]  */
        unsigned int top_obs_rst_req : 1;   /* [5]  */
        unsigned int pll_probe_rst_req : 1; /* [6]  */
        unsigned int reserved_0 : 25;       /* [31..7]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_top_obs_cfg;

/* Define the union u_crg_wdg_ctrl */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int wdg_en : 1;      /* [0]  */
        unsigned int wdg_rst_req : 1; /* [1]  */
        unsigned int reserved_0 : 30; /* [31..2]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_wdg_ctrl;

/* Define the union u_crg_wdg_clr_dly */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int wdg_clr_dly : 27; /* [26..0]  */
        unsigned int reserved_0 : 5;   /* [31..27]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_wdg_clr_dly;

/* Define the union u_crg_rst_wdg_lock */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int rst_wdg_lock : 1; /* [0]  */
        unsigned int reserved_0 : 31;  /* [31..1]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_rst_wdg_lock;

/* Define the union u_crg_wdg_rst_status0 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int up_ring_exception_req : 1;    /* [0]  */
        unsigned int up_ring_lpbx_mode : 1;        /* [1]  */
        unsigned int up_ring_exception_ack : 1;    /* [2]  */
        unsigned int up_ring_exception_active : 1; /* [3]  */
        unsigned int up_cpi_exception_req : 1;     /* [4]  */
        unsigned int up_cpi_lpbx_mode : 1;         /* [5]  */
        unsigned int up_cpi_exception_ack : 1;     /* [6]  */
        unsigned int up_cpi_exception_active : 1;  /* [7]  */
        unsigned int reserved_0 : 7;               /* [14..8]  */
        unsigned int up_wdg_rst_type : 1;          /* [15]  */
        unsigned int reserved_1 : 16;              /* [31..16]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_wdg_rst_status0;

/* Define the union u_crg_wdg_boot_status1 */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int boot_sel_cnt : 15;   /* [14..0]  */
        unsigned int boot_sel_cnt_of : 1; /* [15]  */
        unsigned int boot_sel : 1;        /* [16]  */
        unsigned int reserved_0 : 15;     /* [31..17]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_wdg_boot_status1;

/* Define the union u_crg_htc_clk_en */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int htc_dat_clk_en : 2;      /* [1..0]  */
        unsigned int htc_cfg_clk_en : 1;      /* [2]  */
        unsigned int htc_up_div80_clk_en : 1; /* [3]  */
        unsigned int htc_dp_div90_clk_en : 1; /* [4]  */
        unsigned int htc_dp_div70_clk_en : 1; /* [5]  */
        unsigned int reserved_0 : 26;         /* [31..6]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_htc_clk_en;

/* Define the union u_crg_htc_rst_req */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int htc_dat_rst_req : 2;      /* [1..0]  */
        unsigned int htc_cfg_rst_req : 1;      /* [2]  */
        unsigned int htc_up_div80_rst_req : 1; /* [3]  */
        unsigned int htc_dp_div90_rst_req : 1; /* [4]  */
        unsigned int htc_dp_div70_rst_req : 1; /* [5]  */
        unsigned int reserved_0 : 26;          /* [31..6]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_htc_rst_req;

/* Define the union u_crg_htc_clk_cfg */
typedef union {
    /* Define the struct bits */
    struct {
        unsigned int htc_dp_div90_div_num : 8; /* [7..0]  */
        unsigned int htc_dp_div70_div_num : 8; /* [15..8]  */
        unsigned int reserved_0 : 16;          /* [31..16]  */
    } bits;

    /* Define an unsigned member */
    unsigned int val32;
} u_crg_htc_clk_cfg;


#endif /* C_UNION_DEFINE_CRG_H */
